Not only electronic equipments, but also all the other electronic devices contain a plurality of stabilized DC power supply voltages. The power circuits are disposed in digital circuits, high-frequency circuits and analog circuits, said power circuits having the characteristics suitable for use in these circuits. In a cellular phone, among others, the highest ripple cancellation rate is required because a poor ripple cancellation rate in a power supply of a transmitting section degrades the clarity of the voice conversation. Even in a digitally coded wireless communication means, a carrier signal is modulated and demodulated in an analog manner during the modulation and the demodulation, and therefore the power source ripple noises adversely influence the error rate. As to the cancellation of these ripple noises, for example, the cancellation rate of −80 dB can be achieved by causing a sufficient amount of the operating current of 100 μA to flow. Though some inventions are proposed as described later, there is no proposal that drastically reduces the low operating current and realizes the high ripple cancellation rate.
At present, it is assumed that a few billion of such equipments are operated all over the world. In case one power circuit is operated with 200 μA, it means that the current of 1,000,000 ampere flows in five billion power circuits. In case one power circuit is operated with 3V, it means that the electric power of 3,000 KW is consumed. The prior arts and the circuit theory based on the prior arts will be examined below by referring to the diagrams.
(1) Example of a Conventional Circuit
FIGS. 1 and 2 are a block diagram and a circuit diagram of a CMOS-type stabilized power circuit that has been conventionally used. In FIG. 1, the numerals 1 and 2 indicate voltage supply terminals. The numeral 50 indicates a reference voltage generation circuit that generates a reference voltage Vref. The numeral 60 indicates a circuit that generates a bias current for determining an operating current. The numeral 100 indicates an error amplifier circuit that amplifies an error voltage for the reference voltage Vref. The error amplifier circuit 100 is a two-stage amplifier; a differential circuit 10 is the first stage and a phase inversion amplifier 20 is the second stage. The numeral 40 indicates a circuit that detects a fluctuation of the output voltage and divides the voltage. The concrete example of the conventional stabilized power circuit is shown in the circuit diagram of FIG. 2. The reference voltage generation circuit 50 is connected to an input terminal N1 of the error amplifier, and the output divider circuit 40 is connected to an input terminal N2 of the error amplifier.
FIG. 3 is a graph that shows the DC characteristics in the conventional circuit shown in FIG. 2, showing the dependence on a power supply voltage Vdd by the output voltage Vout and the reference voltage Vref. The horizontal axis indicates the power supply voltage Vdd. The numeral 31 indicate an operating current. The numeral 32 indicates a gate voltage of an output transistor. The numeral 33 indicates the output voltage Vout and the numeral 34 indicates the reference voltage Vref.
FIG. 4 is a 10,000-times-expanded FIG. 3. The numeral 41 indicates the output voltage Vout and the numeral 42 indicates the reference voltage Vref. As shown by the numeral 42, generally, the reference voltage source Vref has a positive source voltage coefficient and has the properties, that as the source voltage rises, the output is increased. These properties are inconvenient for the ripple cancellation rate, whereby particularly the ripple cancellation rate in the low band is to be greatly influenced by the source voltage dependency coefficient of the reference voltage. Though it is not impossible to set the source voltage coefficient to zero, a trimming and a special voltage coefficient element need to be used. Therefore, this requires very great costs in a widely used semiconductor manufacturing method.
(2) Theoretical Formula of the Conventional Circuit
Next, the theory of the output voltage will be examined. The output voltage Vout is represented by the following formula:Vout=Vref*(Av/1+K*Av)+So  (1)
In this formula, Vref indicates the reference voltage, Av represents a voltage gain of the error amplifier, K represents the division ratio of the divider circuit, and So represents a system offset voltage of the error amplifier.
The reference voltage Vref is influenced by the source voltage Vdd. Therefore, the change rate thereof is represented by the source voltage coefficient of Vref, ΔVref=(δVref/δv)/K.
K is the division ratio of an output voltage-division resistance, and K<1. The high PSRR cannot be realized, unless the ripple noise ΔVref derived from Vref is rejected by a filter (PSRR means Power Supply Rejection Ratio, the ratio representing how much the output changes when the source voltage Vdd changes by 1V; for example, if the output changes by 1 mV, PSRR is 1 mV/1V, i.e. −60 db). The ripple noise of Vref contains a very low frequency and a high frequency component, and therefore a large time constant is required for a filter, whereby a filter rejecting all the frequency bands cannot be integrated on the same semiconductor chip.
In FIG. 4, Vref increases by about 10 μV (−100 dB), when Vdd is from 4v to 5v (0 dB). Vout increases by 90 μV:−82 dB).
K indicates the division ratio of the output divider circuit and is represented by the following formula:K=R1/R1+R2
Here, R1 and R2 indicate resistors in the output divider circuit. If these resistors are made by polysilicon, the influence of Vdd can be neglected. Therefore, the rate of change of the source voltage Vdd is not taken into consideration. The value of K is a division value that determines the output voltage. Vref is generally from 0.2 to 0.8, and an extremely small or large value cannot be determined. Thus, this value contributes to the ripple reduction in a limited manner only.
So in the formula (1) represents the system offset voltage, which is unavoidably generated due to the circuit configuration. The system offset voltage is introduced by assuming its existence from an experimental value, on the basis of a way of thinking that has never been conventionally employed. It is empirically known that So is influenced by Vdd, and the formula (1) represents that So has a positive coefficient in most cases and, if a negative coefficient is feasible, So plays an important role.
Here, the source voltage coefficient is represented bySo=δSo/δv.
Av indicates an amplification factor of the entire circuit, has an open-loop gain and has a dependency on the source voltage Vdd as a matter of course. Therefore, the rate of change is represented by the following differential formula:ΔAv=(δAv/δv)/(1+KAv)2
Incidentally, in case Av=10,000 times (80 dB), K=0.5, and the source voltage increases by 1V, 10,000 times is changed into 12,000 times, so that δAv=2,000 times and δV=1v. Thus,ΔAv=80×10−6
When Vref=1.2V, the ripple component is equal to 96 μV (−80.5 dB), and it is clear that it cannot be neglected.
From the above-mentioned examination of the theory, it is clear that the total ripple component of Vout is represented by the following formula (2):ΔVout=ΔVref+Vref*ΔAv+ΔSo  (2)
(3) Examination of Stability
Next, as to the operation stability, the frequency theoretical formula of the gain, the poles and the zero points of each amplifier will be examined (see Analog Integrated Circuit Design, written by David A. Johns and Ken Martin, the first edition, John Wiley & Sons Inc., 1997, pages 223–224).
First, the gain of each amplifier is considered. In FIG. 2, the first stage 10, the second stage 20 and the output circuit 30 also have an amplifying effect. Therefore, assuming that, as seen from the amplifying circuit at the third stage, the voltage gain at each stage is Av1, Av2 and Av3, Av=Av1*Av2*Av3. Assuming that the gain of the ith amplifier stage is Avi, Avi is represented by the following formula (3):Avi=Gmi*Zoi  (3)
Here, Gmi and Zoi are a conductance and an output impedance of the ith stage amplifier, and Zoi=Rpi//Rni//Coi (Rpi//Rni//Coi represents an output resistor of a P transistor i, an output resistor of an N transistor i and a parallel impedance equal to the capacity of an output i). Rpi is represented by the following formula (4) and Gmi is represented by the following formula (5):Rpi=α(Li/Idi)√{square root over ( )}(Vdgi+Vtpi)  (4)
Here, the symbol α indicates a correction coefficient and is approximately 5×106√{square root over ( )}V/m.Gmi=√{square root over ( )}(2 μp Cox(Wi/Li)Idi)  (5)
The symbols μp, Cox, Wi, Li and Idi represent a carrier mobility of a PFET, a unit capacity of a gate oxide, a channel width of a transistor i, a channel length and a drain current, respectively.
Next, the frequency characteristic will be considered.
The amplifier circuits at the first, second and third stages (the output circuit is the amplifier circuit at the third stage), respectively have the poles at the frequency of Fpi.Fpi=½π*Zoi  (6)
As to the outputs of each stage, at the frequency Fpi, the amplification factor starts to be reduced at −6 dB/octave.
From the formula (2), it is clear that the larger amplification factor Av contributes to a reduction of the ripple component of Vout. From the formula (5), it is assumed that the circuit gain becomes higher by making the drain current Idi larger to some extent. On the other hand, according to the formula (4), the drain current Idi is made smaller, so that the output impedance becomes higher and the gain rises. Further, according to the formulae (4) and (5), when the drain current Idi is reduced, the polar frequency is reduced, and the gain is limited and does not reach the high frequency.
At this stage, the stability and the ripple rejection rate are not sufficiently examined, and the frequency characteristic relates to zero points. At the polar frequency, the gain is reduced by the rate of −6 dB/octave and, at the zero-point frequency, the gain rises by the rate of +6 dB/octave. In the normal state, the polar frequency is low and the gain shows an even characteristic.
According to an example of the prior art in FIG. 1, there are two zero points that greatly concern the frequency characteristic of the phase and the gain. The first zero-point frequency Fz1 is determined by an output smoothing capacitor C3 and a load resistance R3.Fz1=½π*R3*C3  (7)
The second zero-point frequency is also very important. The output circuit of the output transistor P4 is connected by a gold wire with the diameter of 25μ–30μ in the integrated power circuit. When its length is from 1 mm to 3 mm, it has a resistance from several 10 mohms to one hundred and several 10 mohms. Both ends of said gold wire that are bonded to a bonding pad and a lead wire have a contact resistance and a parasitic resistance. The total resistance is Rog=100 mohm–200 mohm. The equivalent series resistance ESR of the smoothing output capacitor C3 is also greatly related by the following formula.Fz2=½π*(Rog+ESR)*C3  (8)
(4) Examination of Zero-Point Frequency
C3 is used generally in the range from 1,000 pF to 10 μF. R3 greatly varies in dependence on a load current. For example, in case of about 10 ohm–100 Kohm, Rog=200 mohm and ESR=20 mohm, Fz1=0.15 Hz–1.5 MHz, and Fz2=72 KHz–7.2 MHz. Fz1 moves depending upon the current during the operation. When the load current is large, Fz1 moves to a very high frequency. In case of no load condition, it moves to very low frequency to make a large phase delay, which is likely to cause an unstable state. On the other hand, Fz2 does not depend on the load current, once the values of each section are set. However, the equivalent resistance ESR of the output smoothing capacitor greatly varies depending on the type of the capacitor. Namely, the ESR of a chemical capacitor ranges from a few ohms to a few 10 ohms. The ESR of a tantalum capacitor ranges from one ohm to a few ohms. The ESR of a ceramic capacitor ranges from a few mili-ohms to several 100 mili-ohms. Therefore, a capacitor of a certain type may make the operation unstable.
Fz2 will be explained in detail later and is an important element for the stability, because the phase delay influences the phase characteristic at about 180 degrees.
(5) Examination of Concrete Examples of Stability and Polar Frequency
As for the pole frequency Fpi, it is said that the stability of the stabilized power circuit is stable if the polar frequencies are isolated from each other. For example, it is said that no problem is caused if they are isolated by 10 times. The concrete examples of the polar frequencies at each stage will be examined.
The polar frequency Fp1 at the first stage is Ro1=300K–150K and Co1=0.1–0.2 pF, Fp1=about several 100 KHz–a few MHz. Since the frequency is high, the stability is comparatively unlikely to cause a problem. And, since Co1 is small, the additional capacity for performing the phase compensation can be small, and the position should be suitable choosen for the phase compensation. In FIG. 2, a series circuit comprising a capacity and a resistance is added between the gate and the drain of P3, so that a stable error amplifier can be constructed. However, in the conventional circuit, this phase compensation degrades the PSRR very much. According to the present invention, a sufficient phase compensation is carried out and the PSRR is improved in a canceling signal generation circuit mentioned later. Therefore, a power circuit with the high stability and the low operating current can be realized.
The second polar frequency Fp2 at the second stage is as follows:    Ro2=50K–100K; and    Co2=150 pF–200 pF.Co2 is the sum of the gate capacitance of the output transistor and an additional capacitance C2. While changing in dependence on the output current standard the size of the output transistor, for example, by using a circuit with a large output transistor, a large capacitance should be included in Co2 from the first stage on. Though the second polar frequency Fp2 is approximately fixed during the operation, it becomes important in connection with Fp3 mentioned later.
The third polar frequency Fp3 at the last stage greatly varies during the operation, because Ro3 greatly varies in dependence on the load current. Under the no-load state, Ro3 becomes equal to the output voltage-dividing resistance, is lowered to several 100 Hz when the output voltage-dividing resistance is large, and the phase rotates from the low frequency. Therefore, the phase allowance is reduced and instability may be caused. In order to prevent it from occurring, an idling current is caused to flow through the output voltage-dividing resistance. This is one reason why the circuit current cannot be remarkably reduced.
When the large current flows, the polar frequency Fp3 rises to 150 KHz. At this time, when Fp3 is close to the polar frequency Fp2 and the gain is large, the operation becomes unstable. To avoid the instability, Fp2 needs to be deviated. In the present circuit configuration, Fp2 cannot be higher. According to the countermeasure in the prior art, generally Fp2 is decreased by increasing C2. However, this measure allows the power ripple noises to pass from pd to Vout, because a capacitor of a few pF–a few 10 pF is added to the gate of P4, so that the ripple noise rejection is unavoidably sacrificed thereby. Further, in response to a pulse change, a sufficient amount of operating current needs to flow through P3 for driving the output transistor P4 in order to make the charging and the discharging of the additional capacitor faster.
As described above, according to the conventional circuit configuration, it is inferred from the theoretical formula that: a sufficient operating current and a sufficient idling current are required to flow in order to attain an excellent ripple noise rejection rate (e.g. the characteristic of over −80 dB at 10 Khz) as well as excellent stability.
(6) Simulation Characteristic of the Conventional Circuit
FIGS. 5 and 6 are graphs illustrating the simulation result of the gain phase-frequency characteristics and the PSRR characteristics in the conventional circuit, where the current is high. The curves 51, 52, 53 indicate the gain characteristics of Vout, and the curves 54, 55, 56 indicate the phase characteristics. The curves 61, 62, 63 indicate the PSRR characteristics. The curves 51, 54, 61 indicate the case where the operating current is 100 μA or more. The curves 52, 55, 62 indicate the case where the operating current is 2 μA or less. A phase margin is an index for measuring the stability of a circuit, and it is defined as a phase difference from 180 when the gain is 1. It is said that the phase margin of more than 40 degrees from the 180-degree phase at the frequency with the gain of 1 means a good stability, and there is no oscillation. The gain margin is also an index of the stability of the circuit. It is defined as a reduction ratio of the gain in case the phase of the output signal is delayed by 180 degrees. It is said that, if the gain is reduced by more than 12 dB at the frequency, when the phase of the output is delayed by 180 degrees, it means good stability with no oscillation.
The phase margin will be examined below.
In FIG. 5, the phase curve 54 has the sufficient phase margin of about 50 degrees at the frequency 400 Khz where the phase curve 54 traverses 0 dB. The PSRR curve 61 indicates the PSRR characteristics, when the operating current is sufficiently large, and shows that excellent −90 dB characteristics are attained.
On the other hand, the numerals 52 and 55 show that the curve 55 has already passed 180 degrees, when the curve 52 is 0 dB, that the curve 52 still has the sufficient gain of 40 dB approximately at the frequency 10 Khz where the curve 55 traverses 180 degrees, and that the oscillation occurs approximately at this frequency. Namely, in the conventional circuit, when the operating current is decreased, the phase rotation occurs from the low frequency and the gain is not reduced, so that a stable operation cannot be attained.
The characteristic curves 53, 56 and 62 show the characteristics corresponding to the case where the output capacitance C3 is increased to 100 μF under the condition of an operating current around 2 μA, so that the phase characteristics are improved to enhance the stability. Due to the increase of C3, the 3rd pole Fp3 drastically comes down and the gain decreases by about 20 dB. The 2nd zero-point frequency Fz2 is set between 10 Khz and 100 Khz because of the large C3, to suppress the phase delay and greatly improve the stability. The phase curve 56 shows the phase margin of about 50 degrees in case the gain of the curve 53 is 0 dB. Thus, by adjusting the pole and the zero point, even the conventional circuit system can achieve sufficient stability under the condition of the very low operating current and realize a stabilized power circuit. However, C3 requires a large capacitance value and therefore the conventional circuit cannot be applied to a small apparatus. As a result, there is a problem that the PSRR is drastically decreased. The curve 62 in FIG. 6 indicates the PSRR characteristics corresponding to the curves 53, 56 and shows that the characteristics are degraded by no less than 40 dB or more around the 10 Khz frequency in comparison with the curve 61.
A curve 63 shows, for the purpose of comparison, a PSRR characteristic of the conventional circuit in FIG. 2, where the operating current is 2 μA or less. The circuit has a two-stage amplification structure and therefore an insufficient gain results in poor characteristics.
As described above, it is understood that the conventional circuit system cannot attain the excellent ripple rejection rate, unless the operating current is sufficiently large.
(7) Classification of Prior Arts
There have been many proposals about the ripple rejection in response to increasing market demands for a cellular phone and a wireless LAN. Those are categorized as follows.
(Category 1)
Method by optimization of polar frequency and zero-point frequency, and gain increase (see e.g. U.S. Pat. Nos. 5,631,598 and 6,304,131; JP Patent Application Disclosure Nos. 2001-195138, 2000-284843, 4-263303, and 5-35344)
(Category 2)
Method for operating the reference voltage source and the error amplifier by self stabilized voltage (see e.g. U.S. Pat. No. 5,889,393 and JP Patent Application Disclosure No. 5-204476)
(Category 3)
Method for adaptively controlling the polar frequency and the zero-point frequency under the no-load condition (see e.g. U.S. Pat. No. 6,246,221 and JP Patent Application Disclosure No. 2000-47738)
(Category 4)
Method of rejection by ripple filter (see e.g. JP Patent Application Disclosure No. 8-272461; and U.S. Pat. Nos. 5,130,579 and 4,327,319)
(Category 5)
Method of cancellation by reactor transformer (see e.g. U.S. Pat. Nos. 5,668,464 and JP Patent Application Disclosure No. 2001-339937)
Recently, the invention concerning Category 1 has been often proposed, and has the feature of excellent ripple rejection rate. However, current amplifiers are added to cause an increase of the number of components. And, basically, it applies the scope of the above-mentioned conventional theory. Therefore, the operating current cannot be drastically decreased. This problem still remains unsolved.
In the invention concerning Category 2, the unstable state occurs inevitably in the instant of switching from the original power source to the self-stabilized output at the time of starting-up, so that the time from the starting operation to the stabilization of the output becomes longer. While the invention has been lately applied to a cellular phone, etc., the power source is intermittently operated in order to save electric power, and therefore it is critical, inasfar as that it takes a long time to start up. Further, a precise level shift circuit is required between the error amplifier and the output transistor and the operating current is further increased. Therefore, a low consumption current cannot be realized.
In the invention concerning Category 3, as Category 1, the design theory in the error amplitude is still a conventional one and therefore the operating current cannot be decreased. The load current drastically changes and has the property to contain many noises. And, when the load current is fed back, it prevents the ripple rejection characteristics.
In the invention concerning Category 4, the ripple component contains the frequency band from a few Hz to the high frequency region. Particularly, in order to filter the ripples in the low frequency, the large time constant is indispensable and the integration on a semiconductor substrate cannot be realized without greatly increasing the costs.
In the invention according to Category 5, the large reactor transformer cannot be integrated and the application of this invention is limited.
In order to solve the above-mentioned problems, the present invention has the technical object of providing a ripple rejection circuit having a simple and clear design theory with excellent stability, said circuit having the feature that the various characteristics are not degraded even by decreasing the operating current to 1/100 or less of the conventional operating current and the circuit is not complicated.